The present invention relates to a circuit for dynamically adjusting the width of pulse timing signals.
Pin electronics in automated test equipment (ATE) generally requires capability to adjust a relative timing between rising and falling edges of stimulus pulses driven to a device or system being tested. This adjustment capability, or programmability, allows systematic mismatches and skews in signal propagation characteristics of individual test channels to be compensated for during a pre-test calibration procedure. Thus, the programmability is accessible by control logic or software running on a control processor. The test equipment""s precision is limited by the performance of the timing adjust circuitry so it is critical that this circuitry operate as precisely and predictably as possible.
Referring to FIG. 1, a pulse width adjusting circuit used in current implementations of ATE pin electronics is illustrated generally by numeral 100. The circuit 100 comprises a pair of digitally controlled delay elements D1 and D2, and AND-gate 102, and OR-gate 104, and a multiplexer 106. An input signal IN is coupled to an input of both delay elements D1 and D2. Output A of delay element D1 is coupled to a first input on both the AND-gate 102 and the OR-gate 104. Output B of delay element D2 is coupled to a second input on both the AND-gate 102 and the OR-gate 104. Outputs A1 and B1 from The AND-gate 102 and OR-gate 104, respectively, are coupled to the input of the multiplexer 106.
The delay element D1 delays the input signal IN by a first delay signal Delay1 and the delay element D2 delays the input signal IN by a second delay signal Delay2. The delay signals Delay1 and Delay2 are adjustable to one of S possible settings by an n-bit control word, where nxe2x89xa7log2S. Referring to FIG. 2, the digital delay elements D1 and D2 characteristics are illustrated. Ideally the delay time Td is linear with propagation delay, ranging from a minimum value Tdmin. for a delay control word input value of 0 to a maximum value Tdmax for a delay control word input value of Sxe2x88x921. Each delay element offers a resolution of approximately             Td      max        -          Td      min            S    -    1  
and can be realized in a number of ways. For example, the delay element can be realized using a sequence of digital logic gates in which either a switching current, load capacitance, or path length is controlled by the digital control inputs.
Referring to FIGS. 3a and 3b, timing diagrams for the circuit shown in FIG. 1 are illustrated generally by numeral 300 and 350 respectively. FIG. 3a illustrates the timing for an input signal IN, wherein the timing pulse alters the input signal IN from a low value to a high value for a duration of the timing pulse""s width W and then returns the input signal IN to a low value. As a result this type of pulse is referred to as a xe2x80x9creturn to zeroxe2x80x9d (RTZ) pulse. Conversely, FIG. 3b illustrates the timing for an input signal IN, wherein the timing pulse alters the input signal IN from a high value to a low value for a duration of the timing pulse""s width Wand then returns the input signal IN to a high value. As a result this type of pulse is often to as a xe2x80x9creturn to onexe2x80x9d (RTO) pulse.
The output A of the delay element D1 is the timing pulse delayed by a first delay TD1. The output 13 of the delay element D2 is the tiring pulse delayed by a second delay TD2. A delay difference xcex94t represents the difference between the second delay TD2 and first delay TD1. In the present example, it is assumed that the difference xcex94t is positive. The delayed input signal pulses A and B are recombined using the AND-gate 102 and the OR gate 104. For the RTZ pulse, the output A1 of the AND-gate 102 is a pus having a shortened pulse width of Wxe2x88x92xcex94t. The output B1 of the OR-gate 104 is a pulse having a lengthened pulse width of W+xcex94t. Conversely, for the RTO pulse, the output X of the AND-gate 102 is a pulse having a lengthened pulse width of W+xcex94t. The output Y of the OR-gate 104 is a pulse having a shortened pulse width of Wxe2x88x92xcex94t. For either pulse, the multiplexer 106 selects either the output A1 of the AND-gate 102 or The output B1 of the OR-gate 104 depending on whether the timing pulse is to be shortened or lengthened.
However, the circuit described above suffers from a number of problems that limit its precision, and thus the precision of ATE systems that incorporate it. One of the most significant problems is a difficulty matching the propagation delay through the AND-gate 102 and the OR gate 104 over the circuit operating range of temperature and power supply voltage, as well as expected manufactng tolerances. The uncertainty in mismatch makes it difficult for a control processor to select the delay input values Delay1 and Delay2 and to choose when to switch the multiplexer to maintain a smooth and continuous pulse adjustment performance characteristic. This uncertainty in circuit operating characteristics detracts from The system level functional precision of an ATE system incorporating this type of circuit.
Therefore, there is a need for a circuit that more precisely adjusts the width of an input timing pulse. It is an object of the present invention to obviate or mitigate at least some of the above mentioned disadvantages.
In accordance with an aspect of the present invention, there is provided a method and a circuit for selectively adjusting the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of The input pulse in accordance with a second control input.